1. The Field of the Invention
The present invention relates generally to non-volatile semiconductor memory devices and, more particularly, to an Electrically Erasable Programmable Read Only Memory (EEPROM).
2. Background and Relevant Art
Electronic circuitry has contributed enormously to the advancement of civilization. One of the fundamental building blocks of electronic circuitry is memory. Memory is generally characterized as being volatile or non-volatile. Volatile memory does not retain data between power cycles and requires constant power in order to retain data. Non-volatile memory retains data persistently even across numerous power cycles.
Electrically Erasable and Programmable Read-Only-Memory (EEPROM) is one type of non-volatile memory. An EEPROM is an array or a vector of EEPROM cells. The information is stored in the EEPROM cell as an electrical charge. The electrical charge modifies the electrical characteristics of the EEPROM cell so that the information can be later read back using the modified electrical characteristics. The electrical charge is typically blocked in a trapping layer that gives to the EEPROM cell its memory capability. The electrical charge remains blocked in the trapping layer regardless of power fluctuations or cycling thereby giving the EEPROM cell its non-volatile properties.
The trapping layer is often an isolated floating gate. More recent technologies use other trapping layers such as silicon-nitride or nanocrystals. The trapping layer is isolated from the external world by isolating dielectric layers. The dielectric function is primarily to prevent electrical charge loss from the trapping layer, thereby preventing data loss. One dielectric material in common use in EEPROMs is silicon-dioxide (SiO2) of CMOS technologies. Dedicated processes are often used to improve the performance of the SiO2. Others dielectrics, such as the ONO or High-k, have been recently introduced to improve the isolation.
Information storage requires that the electrical charge pass through one or more dielectric layers to or from the trapping layer. There are a number of different mechanisms used to conventionally pass charge through a dielectric layer for this purpose. Fowler-Nordheim Tunneling is one such mechanism that requires almost no power consumption and rather large voltages across the dielectric. Other mechanisms are based on hot-carrier effects and require large power consumptions and medium voltages across the dielectric.
The reliability of any given EEPROM cell is often critical since many applications can tolerate little, if any, data loss. One important reliability topic is the disturb issue. Disturbs are unwanted modifications of the data stored in untargeted EEPROM cells due to wanted actions on targeted EEPROM cells within the same EEPROM array or vector. Another reliability issue is data retention. Trapped charges in the trapping layer tend to leak away even with no action on the EEPROM cell, sometimes resulting in data loss. A low disturb and high retention EEPROM can thus be highly reliable, thereby significantly reducing the development cost, and thereby increasing the number of applications that the EEPROM may support.
EEPROMs generally have complex and expensive technologies and fabrication processes to fulfill the reliability requirements. Some EEPROMs can be processed with reduced complexity if low cost applications are targeted that require small embedded memory capability. One conventional concept for reducing processing complexity is to have the fabrication process as close as possible to the standard Complementary Metal-Oxide-Semiconductor (CMOS) with few or no added custom steps. One drawback of such low cost EEPROMs is that the resulting EEPROM cell may occupy relatively large layout area in the circuit. This is especially true of single-polysilicon EEPROM cells having only a CMOS gate to form the trapping layer.
Accordingly, what would be advantageous is an EEPROM having EEPROM cells that have high reliability, are not expensive to process, that are low power, and that occupy a reduced layout area.